There is a constant need to increase system resistance against physical attacks. Such attacks generally require a huge number of executions of the same process to reach their target. For example, side-channel resistance characterization requires 1 million curves for DPA. Templates attacks require also in the learning phase a huge number of acquisitions. Fault attacks characterization is performed by scanning the integrated circuit with a laser. The number of laser shots for a single characterization can be ˜100 000 shots.
In order to succeed, these attacks require previous synchronization and specific choice of parameters then used along the set of attacks. Once these first operations are done, the success of the attacks is only a question of time.
Some counter-attack methods are existing as random clock jitter, wait state desynchronization features but those protections are not increasing directly the difficulty to use a huge number of curves.
Some chips are thus implementing features where the clock is randomly changed. Error counters counting security alarms and killing cards after a given number of detections are also known.
Those counter-attack methods do not however provide a satisfying security and further alternative and advantageous solutions would, accordingly, be desirable in the art to be implemented in complement to these previous counter-attack methods.